diff -ur gcc-4.7.2.orig/gcc/doc/cppopts.texi gcc-4.7.2.new/gcc/doc/cppopts.texi
--- gcc-4.7.2.orig/gcc/doc/cppopts.texi	2011-12-20 21:44:13.000000000 +0100
+++ gcc-4.7.2.new/gcc/doc/cppopts.texi	2013-04-03 10:46:44.508597656 +0200
@@ -1,5 +1,5 @@
 @c Copyright (c) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
-@c 2010, Free Software Foundation, Inc.
+@c 2010, 2012, Free Software Foundation, Inc.
 @c This is part of the CPP and GCC manuals.
 @c For copying conditions, see the file gcc.texi.
 
@@ -803,7 +803,7 @@
 Enable special code to work around file systems which only permit very
 short file names, such as MS-DOS@.
 
-@itemx --help
+@item --help
 @itemx --target-help
 @opindex help
 @opindex target-help
diff -ur gcc-4.7.2.orig/gcc/doc/extend.texi gcc-4.7.2.new/gcc/doc/extend.texi
--- gcc-4.7.2.orig/gcc/doc/extend.texi	2012-05-30 16:51:54.000000000 +0200
+++ gcc-4.7.2.new/gcc/doc/extend.texi	2013-04-03 10:46:44.515598546 +0200
@@ -1251,10 +1251,10 @@
 instruction. Pointers to this address space are 16 bits wide.
 
 @item __flash1
-@item __flash2
-@item __flash3
-@item __flash4
-@item __flash5
+@itemx __flash2
+@itemx __flash3
+@itemx __flash4
+@itemx __flash5
 @cindex @code{__flash1} AVR Named Address Spaces
 @cindex @code{__flash2} AVR Named Address Spaces
 @cindex @code{__flash3} AVR Named Address Spaces
diff -ur gcc-4.7.2.orig/gcc/doc/gcc.texi gcc-4.7.2.new/gcc/doc/gcc.texi
--- gcc-4.7.2.orig/gcc/doc/gcc.texi	2010-06-10 01:46:33.000000000 +0200
+++ gcc-4.7.2.new/gcc/doc/gcc.texi	2013-04-03 11:33:22.592219696 +0200
@@ -86,9 +86,13 @@
 @item GNU Press
 @tab Website: www.gnupress.org
 @item a division of the
-@tab General: @tex press@@gnu.org @end tex
+@tab General:
+@tex press@@gnu.org
+@end tex
 @item Free Software Foundation
-@tab Orders:  @tex sales@@gnu.org @end tex
+@tab Orders:
+@tex sales@@gnu.org
+@end tex
 @item 51 Franklin Street, Fifth Floor
 @tab Tel 617-542-5942
 @item Boston, MA 02110-1301 USA
diff -ur gcc-4.7.2.orig/gcc/doc/generic.texi gcc-4.7.2.new/gcc/doc/generic.texi
--- gcc-4.7.2.orig/gcc/doc/generic.texi	2011-12-23 23:07:16.000000000 +0100
+++ gcc-4.7.2.new/gcc/doc/generic.texi	2013-04-03 10:46:44.523599563 +0200
@@ -1,4 +1,4 @@
-@c Copyright (c) 2004, 2005, 2007, 2008, 2010 Free Software Foundation, Inc.
+@c Copyright (c) 2004, 2005, 2007, 2008, 2010, 2012 Free Software Foundation, Inc.
 @c Free Software Foundation, Inc.
 @c This is part of the GCC manual.
 @c For copying conditions, see the file gcc.texi.
@@ -1415,13 +1415,13 @@
 not matter.  The type of the operands and that of the result are
 always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}.
 
-@itemx POINTER_PLUS_EXPR
+@item POINTER_PLUS_EXPR
 This node represents pointer arithmetic.  The first operand is always
 a pointer/reference type.  The second operand is always an unsigned
 integer type compatible with sizetype.  This is the only binary
 arithmetic operand that can operate on pointer types.
 
-@itemx PLUS_EXPR
+@item PLUS_EXPR
 @itemx MINUS_EXPR
 @itemx MULT_EXPR
 These nodes represent various binary arithmetic operations.
diff -ur gcc-4.7.2.orig/gcc/doc/invoke.texi gcc-4.7.2.new/gcc/doc/invoke.texi
--- gcc-4.7.2.orig/gcc/doc/invoke.texi	2012-09-14 22:45:27.000000000 +0200
+++ gcc-4.7.2.new/gcc/doc/invoke.texi	2013-04-03 11:35:10.954992047 +0200
@@ -1592,7 +1592,7 @@
 this will become the default.  The name @samp{gnu9x} is deprecated.
 
 @item gnu11
-@item gnu1x
+@itemx gnu1x
 GNU dialect of ISO C11.  Support is incomplete and experimental.  The
 name @samp{gnu1x} is deprecated.
 
@@ -5179,7 +5179,7 @@
 e.g. With -fdbg-cnt=dce:10,tail_call:0
 dbg_cnt(dce) will return true only for first 10 invocations
 
-@itemx -fenable-@var{kind}-@var{pass}
+@item -fenable-@var{kind}-@var{pass}
 @itemx -fdisable-@var{kind}-@var{pass}=@var{range-list}
 @opindex fdisable-
 @opindex fenable-
@@ -5327,11 +5327,11 @@
 @option{-fdump-rtl-ce3} enable dumping after the three
 if conversion passes.
 
-@itemx -fdump-rtl-cprop_hardreg
+@item -fdump-rtl-cprop_hardreg
 @opindex fdump-rtl-cprop_hardreg
 Dump after hard register copy propagation.
 
-@itemx -fdump-rtl-csa
+@item -fdump-rtl-csa
 @opindex fdump-rtl-csa
 Dump after combining stack adjustments.
 
@@ -5342,11 +5342,11 @@
 @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after
 the two common sub-expression elimination passes.
 
-@itemx -fdump-rtl-dce
+@item -fdump-rtl-dce
 @opindex fdump-rtl-dce
 Dump after the standalone dead code elimination passes.
 
-@itemx -fdump-rtl-dbr
+@item -fdump-rtl-dbr
 @opindex fdump-rtl-dbr
 Dump after delayed branch scheduling.
 
@@ -5391,7 +5391,7 @@
 @opindex fdump-rtl-initvals
 Dump after the computation of the initial value sets.
 
-@itemx -fdump-rtl-into_cfglayout
+@item -fdump-rtl-into_cfglayout
 @opindex fdump-rtl-into_cfglayout
 Dump after converting to cfglayout mode.
 
@@ -5421,7 +5421,7 @@
 @opindex fdump-rtl-rnreg
 Dump after register renumbering.
 
-@itemx -fdump-rtl-outof_cfglayout
+@item -fdump-rtl-outof_cfglayout
 @opindex fdump-rtl-outof_cfglayout
 Dump after converting from cfglayout mode.
 
@@ -5433,7 +5433,7 @@
 @opindex fdump-rtl-postreload
 Dump after post-reload optimizations.
 
-@itemx -fdump-rtl-pro_and_epilogue
+@item -fdump-rtl-pro_and_epilogue
 @opindex fdump-rtl-pro_and_epilogue
 Dump after generating the function prologues and epilogues.
 
@@ -10494,10 +10494,10 @@
 The default is @option{-mfp-mode=caller}
 
 @item -mnosplit-lohi
+@itemx -mno-postinc
+@itemx -mno-postmodify
 @opindex mnosplit-lohi
-@item -mno-postinc
 @opindex mno-postinc
-@item -mno-postmodify
 @opindex mno-postmodify
 Code generation tweaks that disable, respectively, splitting of 32-bit
 loads, generation of post-increment addresses, and generation of
@@ -11344,7 +11344,7 @@
 as needed before the operation.
 
 @item
-If the device supports RAM larger than 64@tie{KiB} and the compiler
+If the device supports RAM larger than 64@tie{}KiB and the compiler
 needs to change @code{RAMPZ} to accomplish an operation, @code{RAMPZ}
 is reset to zero after the operation.
 
@@ -11354,7 +11354,7 @@
 zero in case the ISR code might (implicitly) use it.
 
 @item
-RAM larger than 64@tie{KiB} is not supported by GCC for AVR targets.
+RAM larger than 64@tie{}KiB is not supported by GCC for AVR targets.
 If you use inline assembler to read from locations outside the
 16-bit address range and change one of the @code{RAMP} registers,
 you must reset it to zero after the access.
@@ -11409,7 +11409,7 @@
 memory and if @code{-mshort-calls} is not set.
 
 @item __AVR_HAVE_EIJMP_EICALL__
-@item __AVR_3_BYTE_PC__
+@itemx __AVR_3_BYTE_PC__
 The device has the @code{EIJMP} and @code{EICALL} instructions.
 This is the case for devices with more than 128@tie{}KiB of program memory.
 This also means that the program counter
@@ -11420,13 +11420,13 @@
 with up to 128@tie{}KiB of program memory.
 
 @item __AVR_HAVE_8BIT_SP__
-@item __AVR_HAVE_16BIT_SP__
+@itemx __AVR_HAVE_16BIT_SP__
 The stack pointer (SP) register is treated as 8-bit respectively
 16-bit register by the compiler.
 The definition of these macros is affected by @code{-mtiny-stack}.
 
 @item __AVR_HAVE_SPH__
-@item __AVR_SP8__
+@itemx __AVR_SP8__
 The device has the SPH (high part of stack pointer) special function
 register or has an 8-bit stack pointer, respectively.
 The definition of these macros is affected by @code{-mmcu=} and
@@ -11434,9 +11434,9 @@
 by @code{-msp8}.
 
 @item __AVR_HAVE_RAMPD__
-@item __AVR_HAVE_RAMPX__
-@item __AVR_HAVE_RAMPY__
-@item __AVR_HAVE_RAMPZ__
+@itemx __AVR_HAVE_RAMPX__
+@itemx __AVR_HAVE_RAMPY__
+@itemx __AVR_HAVE_RAMPZ__
 The device has the @code{RAMPD}, @code{RAMPX}, @code{RAMPY},
 @code{RAMPZ} special function register, respectively.
 
@@ -11444,7 +11444,7 @@
 This macro reflects the @code{-mno-interrupts} command line option.
 
 @item __AVR_ERRATA_SKIP__
-@item __AVR_ERRATA_SKIP_JMP_CALL__
+@itemx __AVR_ERRATA_SKIP_JMP_CALL__
 Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit
 instructions because of a hardware erratum.  Skip instructions are
 @code{SBRS}, @code{SBRC}, @code{SBIS}, @code{SBIC} and @code{CPSE}.
@@ -17971,7 +17971,7 @@
 @option{-mhitachi} is given.
 
 @item -mieee
-@item -mno-ieee
+@itemx -mno-ieee
 @opindex mieee
 @opindex mnoieee
 Control the IEEE compliance of floating-point comparisons, which affects the
diff -ur gcc-4.7.2.orig/gcc/doc/md.texi gcc-4.7.2.new/gcc/doc/md.texi
--- gcc-4.7.2.orig/gcc/doc/md.texi	2012-08-27 20:51:44.000000000 +0200
+++ gcc-4.7.2.new/gcc/doc/md.texi	2013-04-03 10:46:44.559604139 +0200
@@ -4405,8 +4405,8 @@
 @cindex @code{ior@var{m}3} instruction pattern
 @cindex @code{xor@var{m}3} instruction pattern
 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
-@item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
-@item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
+@itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
+@itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
diff -ur gcc-4.7.2.orig/gcc/doc/sourcebuild.texi gcc-4.7.2.new/gcc/doc/sourcebuild.texi
--- gcc-4.7.2.orig/gcc/doc/sourcebuild.texi	2011-07-25 18:44:22.000000000 +0200
+++ gcc-4.7.2.new/gcc/doc/sourcebuild.texi	2013-04-03 10:46:44.560604266 +0200
@@ -676,7 +676,7 @@
 @code{lang_checks}.
 
 @table @code
-@itemx all.cross
+@item all.cross
 @itemx start.encap
 @itemx rest.encap
 FIXME: exactly what goes in each of these targets?
diff -ur gcc-4.7.2.orig/gcc/doc/tm.texi gcc-4.7.2.new/gcc/doc/tm.texi
--- gcc-4.7.2.orig/gcc/doc/tm.texi	2012-08-10 15:21:31.000000000 +0200
+++ gcc-4.7.2.new/gcc/doc/tm.texi	2013-04-03 10:46:39.783997184 +0200
@@ -11366,7 +11366,8 @@
 value of @code{TARGET_CONST_ANCHOR} is a power of 2.  For example, on
 MIPS, where add-immediate takes a 16-bit signed value,
 @code{TARGET_CONST_ANCHOR} is set to @samp{0x8000}.  The default value
-is zero, which disables this optimization.  @end deftypevr
+is zero, which disables this optimization.
+@end deftypevr
 
 @deftypevr {Target Hook} {unsigned char} TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
 This value should be set if the result written by @code{atomic_test_and_set} is not exactly 1, i.e. the @code{bool} @code{true}.
diff -ur gcc-4.7.2.orig/gcc/doc/tm.texi.in gcc-4.7.2.new/gcc/doc/tm.texi.in
--- gcc-4.7.2.orig/gcc/doc/tm.texi.in	2012-08-10 15:21:31.000000000 +0200
+++ gcc-4.7.2.new/gcc/doc/tm.texi.in	2013-04-03 10:46:39.816001251 +0200
@@ -11238,6 +11238,7 @@
 value of @code{TARGET_CONST_ANCHOR} is a power of 2.  For example, on
 MIPS, where add-immediate takes a 16-bit signed value,
 @code{TARGET_CONST_ANCHOR} is set to @samp{0x8000}.  The default value
-is zero, which disables this optimization.  @end deftypevr
+is zero, which disables this optimization.
+@end deftypevr
 
 @hook TARGET_ATOMIC_TEST_AND_SET_TRUEVAL